IPC, Context-Switch and Syscall Performance#

With L4Re being a microkernel-based system and hypervisor, some of you are interested in the IPC and syscall performance of L4Re as well as the performance of context switches. IPC is a base-level communication mechanisms that allows to exchange a limited amount of payload data between two threads. Context switching is switching from one executing thread to another, which sending a message is exactly doing. The fastest IPC is between two threads running in the same address space (task) on the same CPU core (Intra). Inter is IPC between two address spaces. A syscall is also an IPC but only communicates with the kernel.

The following table provides IPC performance numbers for a single IPC on various popular platforms (average over multiple ten thousand calls). To perform the measurement, the L4Re microkernel has been configured in its performance configuration CONFIG_PERFORMANCE=y, i.e., without assertions.

The source code of the benchmark program can be found here. The images used to measure those are linked in the table below.

Numbers are measured with the performance counters. On Arm, the cycle counter is used. On x86, the fixed-function counters are used.

For x86: You can boot the image directly in GRUB2, e.g. multiboot2 (http,l4re.org)/download/ipcbench/amd64/l4re_ipcbench-20250602.elf

For the Raspberry Pi’s, converting the uimage to a raw image for firmware boot works like this: dd if=l4re_ipcbench_rpi5-elX.uimage of=l4re.raw bs=64 skip=1.

Plots of Parallel Execution of the Benchmark#

Intra space IPC core-local IPC and system calls, parallel on cores